ChrisOS Research Project Technical systems documentation

Learning path and prerequisites

In this chapter

The sequence organizes the corpus into levels, modules and chapters. A missing entry is an explicit gap, not a published chapter. Word count is only an editorial signal, not evidence of mastery or technical completeness. Level and module headings link to the first authored chapter in that section.

Learning map

01 · Matter, mathematical tools, electricity, devices and logic

Matter and physical models

No. Chapter State Prerequisites Previous in sequence
1 Matter, atoms, charge and physical models Text floor met; technical review required — —

Mathematical tools for physical systems

No. Chapter State Prerequisites Previous in sequence
2 Vectors and complex numbers for systems Text floor met; technical review required Matter, atoms, charge and physical models Matter, atoms, charge and physical models

Charge, circuits and electromagnetic behavior

No. Chapter State Prerequisites Previous in sequence
3 Electric charge, field, potential and energy Text floor met; technical review required Matter, atoms, charge and physical models; Vectors and complex numbers for systems Vectors and complex numbers for systems
4 Voltage, current, resistance, energy and power Text floor met; technical review required Electric charge, field, potential and energy Electric charge, field, potential and energy
5 Ohm's law, Kirchhoff's laws and circuit analysis Text floor met; technical review required Voltage, current, resistance, energy and power Voltage, current, resistance, energy and power
6 Capacitance, inductance and stored field energy Text floor met; technical review required Ohm's law, Kirchhoff's laws and circuit analysis Ohm's law, Kirchhoff's laws and circuit analysis
7 RC, RL and RLC transients Text floor met; technical review required Capacitance, inductance and stored field energy Capacitance, inductance and stored field energy
8 AC signals, phase, frequency and impedance Text floor met; technical review required RC, RL and RLC transients; Vectors and complex numbers for systems RC, RL and RLC transients
9 Electromagnetic induction and transformers Text floor met; technical review required AC signals, phase, frequency and impedance; Capacitance, inductance and stored field energy AC signals, phase, frequency and impedance
10 Transmission lines and differential signaling Text floor met; technical review required Electromagnetic induction and transformers; AC signals, phase, frequency and impedance Electromagnetic induction and transformers
11 Noise, grounding and signal integrity Text floor met; technical review required Transmission lines and differential signaling; AC signals, phase, frequency and impedance Transmission lines and differential signaling
12 Power delivery, regulation and decoupling Text floor met; technical review required Noise, grounding and signal integrity; AC signals, phase, frequency and impedance; RC, RL and RLC transients Noise, grounding and signal integrity

Semiconductor devices and electrical logic

No. Chapter State Prerequisites Previous in sequence
13 Crystal structure, energy bands and doping Text floor met; technical review required Matter, atoms, charge and physical models; Electric charge, field, potential and energy Power delivery, regulation and decoupling
14 P-N junctions and semiconductor interfaces Text floor met; technical review required Crystal structure, energy bands and doping; Electric charge, field, potential and energy Crystal structure, energy bands and doping
15 MOS capacitor electrostatics Text floor met; technical review required Crystal structure, energy bands and doping; P-N junctions and semiconductor interfaces; Electric charge, field, potential and energy; Capacitance, inductance and stored field energy P-N junctions and semiconductor interfaces
16 Transistors and CMOS logic Text floor met; technical review required MOS capacitor electrostatics; P-N junctions and semiconductor interfaces MOS capacitor electrostatics
17 CMOS switching, delay and power Text floor met; technical review required MOS capacitor electrostatics; Transistors and CMOS logic; Capacitance, inductance and stored field energy; Power delivery, regulation and decoupling Transistors and CMOS logic
18 Logic levels, thresholds, fan-out and noise margins Text floor met; technical review required Transistors and CMOS logic; CMOS switching, delay and power; Noise, grounding and signal integrity CMOS switching, delay and power

Boolean and numerical logic

No. Chapter State Prerequisites Previous in sequence
19 Boolean algebra and logic representation Text floor met; technical review required Logic levels, thresholds, fan-out and noise margins Logic levels, thresholds, fan-out and noise margins
20 Number systems and binary arithmetic Text floor met; technical review required Boolean algebra and logic representation Boolean algebra and logic representation
21 Combinational circuits Text floor met; technical review required Boolean algebra and logic representation; Transistors and CMOS logic Number systems and binary arithmetic
22 Adders, ALUs and finite-width arithmetic Text floor met; technical review required Combinational circuits; Number systems and binary arithmetic Combinational circuits

State, time and memory cells

No. Chapter State Prerequisites Previous in sequence
23 Logic, state and sequential circuits Text floor met; technical review required Combinational circuits Adders, ALUs and finite-width arithmetic
24 Latches, flip-flops and metastability Text floor met; technical review required Logic, state and sequential circuits; Transistors and CMOS logic Logic, state and sequential circuits
25 Registers, counters and state transitions Text floor met; technical review required Latches, flip-flops and metastability; Adders, ALUs and finite-width arithmetic Latches, flip-flops and metastability
26 Clocking, propagation delay and the meaning of time Text floor met; technical review required Latches, flip-flops and metastability; RC, RL and RLC transients; Transistors and CMOS logic Registers, counters and state transitions
27 SRAM, DRAM and the memory abstraction used by ChrisOS Text floor met; technical review required Latches, flip-flops and metastability; Clocking, propagation delay and the meaning of time; Transistors and CMOS logic; Capacitance, inductance and stored field energy Clocking, propagation delay and the meaning of time

02 · Mathematical tools, representation and algorithms

Mathematical language for discrete systems

No. Chapter State Prerequisites Previous in sequence
28 Discrete mathematics: sets, relations and functions Text floor met; technical review required Boolean algebra and logic representation; Number systems and binary arithmetic SRAM, DRAM and the memory abstraction used by ChrisOS
29 Proof, invariants and induction for systems Text floor met; technical review required Discrete mathematics: sets, relations and functions Discrete mathematics: sets, relations and functions

Bits, types and layout

No. Chapter State Prerequisites Previous in sequence
30 Data representation, memory layout and pointers Text floor met; technical review required Number systems and binary arithmetic; Registers, counters and state transitions Proof, invariants and induction for systems

Complexity and algorithmic reasoning

No. Chapter State Prerequisites Previous in sequence
31 Algorithm analysis and systems cost models Text floor met; technical review required Data representation, memory layout and pointers; Proof, invariants and induction for systems Data representation, memory layout and pointers
32 Recursion, recurrences and amortized analysis Text floor met; technical review required Algorithm analysis and systems cost models; Proof, invariants and induction for systems Algorithm analysis and systems cost models

Data structures

No. Chapter State Prerequisites Previous in sequence
33 Data structures for systems software Text floor met; technical review required Data representation, memory layout and pointers; Algorithm analysis and systems cost models Recursion, recurrences and amortized analysis
34 Arrays, linked structures, stacks and queues Text floor met; technical review required Data structures for systems software; Recursion, recurrences and amortized analysis Data structures for systems software
35 Hash tables, hashing and bounded symbol lookup Text floor met; technical review required Arrays, linked structures, stacks and queues; Algorithm analysis and systems cost models Arrays, linked structures, stacks and queues
36 Trees, binary heaps and tries Text floor met; technical review required Arrays, linked structures, stacks and queues; Recursion, recurrences and amortized analysis Hash tables, hashing and bounded symbol lookup
37 Graphs, connectivity and union-find Text floor met; technical review required Arrays, linked structures, stacks and queues; Trees, binary heaps and tries; Algorithm analysis and systems cost models; Proof, invariants and induction for systems Trees, binary heaps and tries
38 Bitmaps, ring buffers and free-list patterns Text floor met; technical review required Arrays, linked structures, stacks and queues; Algorithm analysis and systems cost models Graphs, connectivity and union-find

Algorithms used by systems software

No. Chapter State Prerequisites Previous in sequence
39 Sorting and searching algorithms Text floor met; technical review required Algorithm analysis and systems cost models; Arrays, linked structures, stacks and queues; Recursion, recurrences and amortized analysis; Trees, binary heaps and tries Bitmaps, ring buffers and free-list patterns
40 Graph algorithms for systems software Text floor met; technical review required Graphs, connectivity and union-find; Arrays, linked structures, stacks and queues; Trees, binary heaps and tries; Algorithm analysis and systems cost models; Sorting and searching algorithms Sorting and searching algorithms
41 String and parsing algorithms Text floor met; technical review required Data representation, memory layout and pointers; Algorithm analysis and systems cost models; Recursion, recurrences and amortized analysis; Sorting and searching algorithms Graph algorithms for systems software
42 Algorithms used by ChrisOS Text floor met; technical review required Data structures for systems software; Algorithm analysis and systems cost models String and parsing algorithms

03 · Instruction execution and platform

Datapath, microarchitecture and ISA

No. Chapter State Prerequisites Previous in sequence
43 CPU datapath and instruction-set architecture Text floor met; technical review required Logic, state and sequential circuits; Registers, counters and state transitions; Adders, ALUs and finite-width arithmetic Algorithms used by ChrisOS
44 CPU microarchitecture and pipelining Text floor met; technical review required CPU datapath and instruction-set architecture; Clocking, propagation delay and the meaning of time; Registers, counters and state transitions CPU datapath and instruction-set architecture
45 Pipeline hazards, interlocks and forwarding Text floor met; technical review required CPU microarchitecture and pipelining; CPU datapath and instruction-set architecture CPU microarchitecture and pipelining
46 Branch prediction and speculative execution Text floor met; technical review required CPU microarchitecture and pipelining; Pipeline hazards, interlocks and forwarding Pipeline hazards, interlocks and forwarding
47 Out-of-order execution, register renaming and retirement Text floor met; technical review required Pipeline hazards, interlocks and forwarding; Branch prediction and speculative execution Branch prediction and speculative execution

Machine code and x86-64 encoding

No. Chapter State Prerequisites Previous in sequence
48 Machine code, assembly and relocatable meaning Text floor met; technical review required CPU datapath and instruction-set architecture; Data representation, memory layout and pointers Out-of-order execution, register renaming and retirement
49 x86-64 registers, aliases and flags Text floor met; technical review required CPU datapath and instruction-set architecture; Adders, ALUs and finite-width arithmetic; Registers, counters and state transitions Machine code, assembly and relocatable meaning
50 x86 instruction encoding and bounded decoding Text floor met; technical review required Machine code, assembly and relocatable meaning; x86-64 registers, aliases and flags x86-64 registers, aliases and flags

Addressing and protection

No. Chapter State Prerequisites Previous in sequence
51 x86-64 memory, privilege and architectural state Text floor met; technical review required CPU datapath and instruction-set architecture; x86-64 registers, aliases and flags; x86 instruction encoding and bounded decoding x86 instruction encoding and bounded decoding
52 Privilege rings, controlled entry and protection boundaries Text floor met; technical review required x86-64 memory, privilege and architectural state x86-64 memory, privilege and architectural state

Memory hierarchy and concurrency

No. Chapter State Prerequisites Previous in sequence
53 DRAM organization and memory controllers Text floor met; technical review required SRAM, DRAM and the memory abstraction used by ChrisOS; Transmission lines and differential signaling; Buses, memory-mapped I/O and DMA; Caches and memory hierarchy Privilege rings, controlled entry and protection boundaries
54 Caches and memory hierarchy Text floor met; technical review required CPU datapath and instruction-set architecture; x86-64 memory, privilege and architectural state DRAM organization and memory controllers
55 Cache coherence and multiprocessor memory Text floor met; technical review required Caches and memory hierarchy; x86-64 memory, privilege and architectural state Caches and memory hierarchy
56 Atomic operations and the memory model Text floor met; technical review required Cache coherence and multiprocessor memory; Caches and memory hierarchy; CPU datapath and instruction-set architecture Cache coherence and multiprocessor memory

Devices and platform discovery

No. Chapter State Prerequisites Previous in sequence
57 Buses, memory-mapped I/O and DMA Text floor met; technical review required x86-64 memory, privilege and architectural state; Caches and memory hierarchy; Atomic operations and the memory model Atomic operations and the memory model
58 PCI and PCI Express Text floor met; technical review required Buses, memory-mapped I/O and DMA; x86-64 memory, privilege and architectural state Buses, memory-mapped I/O and DMA
59 ACPI and platform description Text floor met; technical review required PCI and PCI Express; x86-64 memory, privilege and architectural state PCI and PCI Express

04 · From reset to kernel entry

Firmware and boot contracts

No. Chapter State Prerequisites Previous in sequence
60 Reset, CPU startup and firmware Text floor met; technical review required ACPI and platform description; x86-64 registers, aliases and flags; x86-64 memory, privilege and architectural state ACPI and platform description
61 UEFI Text floor met; technical review required Reset, CPU startup and firmware Reset, CPU startup and firmware
62 Limine boot protocol Text floor met; technical review required UEFI; Reset, CPU startup and firmware UEFI
63 Boot information, normalization and ownership Text floor met; technical review required Limine boot protocol Limine boot protocol

Executable layout and entry

No. Chapter State Prerequisites Previous in sequence
64 ELF64, object linking and the ChrisOS kernel image Text floor met; technical review required Boot information, normalization and ownership; Machine code, assembly and relocatable meaning; x86-64 memory, privilege and architectural state Boot information, normalization and ownership
65 GNU ld linker scripts and the ChrisOS kernel layout Text floor met; technical review required ELF64, object linking and the ChrisOS kernel image ELF64, object linking and the ChrisOS kernel image
66 Higher-half kernels, canonical addresses and ChrisOS Text floor met; technical review required GNU ld linker scripts and the ChrisOS kernel layout; x86-64 memory, privilege and architectural state; Limine boot protocol; Boot information, normalization and ownership GNU ld linker scripts and the ChrisOS kernel layout
67 From power-on to kstart: the complete ChrisOS boot handoff Text floor met; technical review required Reset, CPU startup and firmware; UEFI; Limine boot protocol; Boot information, normalization and ownership; ELF64, object linking and the ChrisOS kernel image; GNU ld linker scripts and the ChrisOS kernel layout; Higher-half kernels, canonical addresses and ChrisOS Higher-half kernels, canonical addresses and ChrisOS

05 · Kernel, memory and execution contexts

Trust boundaries and exception entry

No. Chapter State Prerequisites Previous in sequence
68 Kernel model, protection domains and trust boundaries Text floor met; technical review required From power-on to kstart: the complete ChrisOS boot handoff; x86-64 memory, privilege and architectural state From power-on to kstart: the complete ChrisOS boot handoff
69 GDT and TSS Text floor met; technical review required x86-64 memory, privilege and architectural state; Privilege rings, controlled entry and protection boundaries Kernel model, protection domains and trust boundaries
70 IDT, exception entry and interrupt frames Text floor met; technical review required GDT and TSS; x86-64 memory, privilege and architectural state GDT and TSS
71 PIC, Local APIC and IOAPIC routing Text floor met; technical review required IDT, exception entry and interrupt frames; Buses, memory-mapped I/O and DMA IDT, exception entry and interrupt frames
72 PIT timing and scheduler tick semantics Text floor met; technical review required PIC, Local APIC and IOAPIC routing; IDT, exception entry and interrupt frames PIC, Local APIC and IOAPIC routing
73 Panic, serial diagnostics and kernel log Text floor met; technical review required IDT, exception entry and interrupt frames PIT timing and scheduler tick semantics

Frames and address translation

No. Chapter State Prerequisites Previous in sequence
74 Physical memory management Text floor met; technical review required Matter, atoms, charge and physical models; x86-64 memory, privilege and architectural state Panic, serial diagnostics and kernel log
75 Higher-half direct map Text floor met; technical review required Boot information, normalization and ownership; x86-64 memory, privilege and architectural state; Physical memory management Physical memory management
76 PMM allocation algorithms and invariants Text floor met; technical review required Physical memory management; Data structures for systems software; Algorithm analysis and systems cost models Higher-half direct map
77 Virtual memory and address-space construction Text floor met; technical review required Physical memory management; Higher-half direct map; x86-64 memory, privilege and architectural state PMM allocation algorithms and invariants
78 x86-64 page-table layout and entry semantics Text floor met; technical review required Virtual memory and address-space construction; x86-64 memory, privilege and architectural state Virtual memory and address-space construction
79 Page faults: architectural semantics and ChrisOS recovery paths Text floor met; technical review required Virtual memory and address-space construction; x86-64 page-table layout and entry semantics; IDT, exception entry and interrupt frames x86-64 page-table layout and entry semantics
80 Process address spaces and virtual-memory layout Text floor met; technical review required Virtual memory and address-space construction; x86-64 page-table layout and entry semantics; Page faults: architectural semantics and ChrisOS recovery paths Page faults: architectural semantics and ChrisOS recovery paths
81 Translation Lookaside Buffer: cached translation, invalidation and ChrisOS Text floor met; technical review required Virtual memory and address-space construction; x86-64 page-table layout and entry semantics; Process address spaces and virtual-memory layout Process address spaces and virtual-memory layout

Concurrency and ownership

No. Chapter State Prerequisites Previous in sequence
82 Interrupts and symmetric multiprocessing Text floor met; technical review required x86-64 memory, privilege and architectural state; Kernel model, protection domains and trust boundaries; IDT, exception entry and interrupt frames Translation Lookaside Buffer: cached translation, invalidation and ChrisOS
83 TLB shootdown, CPU fencing and safe physical-frame reclamation Text floor met; technical review required Translation Lookaside Buffer: cached translation, invalidation and ChrisOS; Interrupts and symmetric multiprocessing; Virtual memory and address-space construction Interrupts and symmetric multiprocessing
84 Kernel heap, ownership and allocation lifetime Text floor met; technical review required Physical memory management; PMM allocation algorithms and invariants; Higher-half direct map TLB shootdown, CPU fencing and safe physical-frame reclamation
85 Spinlocks, interrupt exclusion and lock ordering Text floor met; technical review required Atomic operations and the memory model; Interrupts and symmetric multiprocessing Kernel heap, ownership and allocation lifetime
86 Resource lifetime, teardown and safe reclamation Text floor met; technical review required Kernel heap, ownership and allocation lifetime; Spinlocks, interrupt exclusion and lock ordering; TLB shootdown, CPU fencing and safe physical-frame reclamation Spinlocks, interrupt exclusion and lock ordering
87 Kernel jobs and cooperative kernel threads Text floor met; technical review required Interrupts and symmetric multiprocessing; Atomic operations and the memory model Resource lifetime, teardown and safe reclamation
88 Executable memory, JIT aliases and W^X Text floor met; technical review required Virtual memory and address-space construction; Translation Lookaside Buffer: cached translation, invalidation and ChrisOS; TLB shootdown, CPU fencing and safe physical-frame reclamation; Resource lifetime, teardown and safe reclamation; Spinlocks, interrupt exclusion and lock ordering Kernel jobs and cooperative kernel threads

User execution and process lifecycle

No. Chapter State Prerequisites Previous in sequence
89 User-mode entry and controlled return to ring 0 Text floor met; technical review required GDT and TSS; Virtual memory and address-space construction Executable memory, JIT aliases and W^X
90 Native processes and system calls Text floor met; technical review required Virtual memory and address-space construction; Kernel model, protection domains and trust boundaries; User-mode entry and controlled return to ring 0 User-mode entry and controlled return to ring 0
91 Safe user-memory access Text floor met; technical review required Virtual memory and address-space construction; User-mode entry and controlled return to ring 0 Native processes and system calls
92 Process lifecycle and state Text floor met; technical review required Virtual memory and address-space construction; Physical memory management; User-mode entry and controlled return to ring 0 Safe user-memory access

06 · Languages, compilers and runtimes

Compiler construction

No. Chapter State Prerequisites Previous in sequence
93 Compiler construction pipeline in ChrisOS Text floor met; technical review required CPU datapath and instruction-set architecture; Machine code, assembly and relocatable meaning; x86 instruction encoding and bounded decoding; ELF64, object linking and the ChrisOS kernel image Process lifecycle and state
94 Lexical analysis Text floor met; technical review required Compiler construction pipeline in ChrisOS; String and parsing algorithms Compiler construction pipeline in ChrisOS
95 Parsing and grammars Text floor met; technical review required Compiler construction pipeline in ChrisOS; Lexical analysis; String and parsing algorithms Lexical analysis
96 Semantic analysis and type systems Text floor met; technical review required Compiler construction pipeline in ChrisOS; Lexical analysis; Parsing and grammars; Data representation, memory layout and pointers Parsing and grammars
97 Intermediate representations Text floor met; technical review required Compiler construction pipeline in ChrisOS; Parsing and grammars; Semantic analysis and type systems Semantic analysis and type systems
98 Native code generation Text floor met; technical review required Intermediate representations; Semantic analysis and type systems; x86 instruction encoding and bounded decoding; ELF64, object linking and the ChrisOS kernel image Intermediate representations
99 Calling conventions and stack frames Text floor met; technical review required Intermediate representations; Native code generation Native code generation

ChrisC and CLVM execution

No. Chapter State Prerequisites Previous in sequence
100 ChrisC and the CLVM execution model Text floor met; technical review required Compiler construction pipeline in ChrisOS; Intermediate representations; Calling conventions and stack frames Calling conventions and stack frames
101 CLVM bytecode format and instruction set Text floor met; technical review required ChrisC and the CLVM execution model ChrisC and the CLVM execution model
102 CLVM memory, allocation and isolation Text floor met; technical review required ChrisC and the CLVM execution model; CLVM bytecode format and instruction set CLVM bytecode format and instruction set
103 CLVM syscalls and host-service ABI Text floor met; technical review required CLVM bytecode format and instruction set; CLVM memory, allocation and isolation CLVM memory, allocation and isolation
104 CLVM interpreter architecture and execution model Text floor met; technical review required CLVM bytecode format and instruction set; CLVM memory, allocation and isolation; CLVM syscalls and host-service ABI CLVM syscalls and host-service ABI
105 CLVM JIT architecture and native execution Text floor met; technical review required CLVM bytecode format and instruction set; CLVM interpreter architecture and execution model; CLVM memory, allocation and isolation CLVM interpreter architecture and execution model
106 Debugger, source maps and execution control Text floor met; technical review required CLVM interpreter architecture and execution model; CLVM JIT architecture and native execution; ChrisC and the CLVM execution model CLVM JIT architecture and native execution
107 Libraries, modules and garbage collection Text floor met; technical review required CLVM memory, allocation and isolation; CLVM syscalls and host-service ABI; CLVM interpreter architecture and execution model; Debugger, source maps and execution control Debugger, source maps and execution control

Native toolchain

No. Chapter State Prerequisites Previous in sequence
108 Native toolchain: KCC, ChrisAsm, ChrisO and ChrisLd Text floor met; technical review required Compiler construction pipeline in ChrisOS; Native code generation; x86 instruction encoding and bounded decoding; ELF64, object linking and the ChrisOS kernel image Libraries, modules and garbage collection
109 KCC architecture and C profile Text floor met; technical review required Native toolchain: KCC, ChrisAsm, ChrisO and ChrisLd; Semantic analysis and type systems; Native code generation; Calling conventions and stack frames; x86 instruction encoding and bounded decoding Native toolchain: KCC, ChrisAsm, ChrisO and ChrisLd
110 ChrisAsm Text floor met; technical review required Native toolchain: KCC, ChrisAsm, ChrisO and ChrisLd; Machine code, assembly and relocatable meaning; x86 instruction encoding and bounded decoding; Calling conventions and stack frames KCC architecture and C profile
111 ChrisO object format Text floor met; technical review required Native toolchain: KCC, ChrisAsm, ChrisO and ChrisLd; Data representation, memory layout and pointers; ELF64, object linking and the ChrisOS kernel image ChrisAsm
112 ChrisLd Text floor met; technical review required Native toolchain: KCC, ChrisAsm, ChrisO and ChrisLd; ChrisO object format; ChrisAsm; ELF64, object linking and the ChrisOS kernel image; Calling conventions and stack frames ChrisO object format

07 · Persistent state and filesystems

Block transport and media

No. Chapter State Prerequisites Previous in sequence
113 Block storage stack Text floor met; technical review required Buses, memory-mapped I/O and DMA; PCI and PCI Express; Physical memory management ChrisLd
114 ATA PIO and Bus Master IDE DMA Text floor met; technical review required Block storage stack; Buses, memory-mapped I/O and DMA; PCI and PCI Express; Interrupts and symmetric multiprocessing; Physical memory management Block storage stack
115 AHCI and SATA Text floor met; technical review required Block storage stack; Buses, memory-mapped I/O and DMA; PCI and PCI Express; Physical memory management ATA PIO and Bus Master IDE DMA
116 NVMe queues and namespaces Text floor met; technical review required Block storage stack; Buses, memory-mapped I/O and DMA; PCI and PCI Express; Physical memory management AHCI and SATA
117 VirtIO Block Text floor met; technical review required Block storage stack; Buses, memory-mapped I/O and DMA; PCI and PCI Express; Physical memory management NVMe queues and namespaces
118 USB mass storage and host controllers Text floor met; technical review required Block storage stack; Buses, memory-mapped I/O and DMA; PCI and PCI Express; Physical memory management VirtIO Block
119 Partition tables and GPT Text floor met; technical review required Block storage stack; ATA PIO and Bus Master IDE DMA; AHCI and SATA; NVMe queues and namespaces; VirtIO Block; USB mass storage and host controllers USB mass storage and host controllers

ChrisFS structures and recovery

No. Chapter State Prerequisites Previous in sequence
120 ChrisFS architecture: layout, allocation, journaling and validation Text floor met; technical review required Block storage stack; Partition tables and GPT; Resource lifetime, teardown and safe reclamation; Spinlocks, interrupt exclusion and lock ordering Partition tables and GPT
121 ChrisFS superblock and volume geometry Text floor met; technical review required ChrisFS architecture: layout, allocation, journaling and validation; Block storage stack; Partition tables and GPT ChrisFS architecture: layout, allocation, journaling and validation
122 ChrisFS inodes and block indirection Text floor met; technical review required ChrisFS architecture: layout, allocation, journaling and validation; ChrisFS superblock and volume geometry ChrisFS superblock and volume geometry
123 ChrisFS directories and path resolution Text floor met; technical review required ChrisFS architecture: layout, allocation, journaling and validation; ChrisFS inodes and block indirection ChrisFS inodes and block indirection
124 ChrisFS journaling and recovery Text floor met; technical review required ChrisFS architecture: layout, allocation, journaling and validation; ChrisFS superblock and volume geometry; ChrisFS inodes and block indirection; ChrisFS directories and path resolution ChrisFS directories and path resolution
125 ChrisFS cache and block allocation Text floor met; technical review required ChrisFS architecture: layout, allocation, journaling and validation; ChrisFS superblock and volume geometry; ChrisFS inodes and block indirection; ChrisFS journaling and recovery ChrisFS journaling and recovery
126 ChrisFS consistency checking and corruption detection Text floor met; technical review required ChrisFS architecture: layout, allocation, journaling and validation; ChrisFS superblock and volume geometry; ChrisFS inodes and block indirection; ChrisFS directories and path resolution; ChrisFS journaling and recovery; ChrisFS cache and block allocation ChrisFS cache and block allocation

08 · From bytes to the desktop

Pixel memory and composition

No. Chapter State Prerequisites Previous in sequence
127 Pixels, framebuffer memory and presentation Text floor met; technical review required Data representation, memory layout and pointers; Buses, memory-mapped I/O and DMA; Kernel heap, ownership and allocation lifetime ChrisFS consistency checking and corruption detection
128 Color formats and alpha Text floor met; technical review required Pixels, framebuffer memory and presentation; Data representation, memory layout and pointers Pixels, framebuffer memory and presentation
129 2D primitives and composition Text floor met; technical review required Pixels, framebuffer memory and presentation; Color formats and alpha; Algorithm analysis and systems cost models Color formats and alpha
130 Desktop composition Text floor met; technical review required Pixels, framebuffer memory and presentation; Color formats and alpha; 2D primitives and composition 2D primitives and composition

Input, windows and applications

No. Chapter State Prerequisites Previous in sequence
131 Desktop, windows and applications Text floor met; technical review required Pixels, framebuffer memory and presentation; ChrisC and the CLVM execution model Desktop composition
132 Window manager and task model Text floor met; technical review required Desktop, windows and applications; 2D primitives and composition; Desktop composition Desktop, windows and applications
133 Input routing, focus and capture Text floor met; technical review required Window manager and task model; Desktop, windows and applications; Interrupts and symmetric multiprocessing Window manager and task model
134 ChrisEditor: a self-hosted modal editor Text floor met; technical review required Input routing, focus and capture; Window manager and task model; Desktop, windows and applications; ChrisC and the CLVM execution model; ChrisFS architecture: layout, allocation, journaling and validation Input routing, focus and capture
135 ChrisShell: the graphical command environment Text floor met; technical review required Input routing, focus and capture; Window manager and task model; Desktop, windows and applications; ChrisC and the CLVM execution model; ChrisFS architecture: layout, allocation, journaling and validation ChrisEditor: a self-hosted modal editor
136 File Manager: ChrisOS Explorer Text floor met; technical review required Input routing, focus and capture; Window manager and task model; Desktop, windows and applications; ChrisEditor: a self-hosted modal editor; ChrisFS architecture: layout, allocation, journaling and validation ChrisShell: the graphical command environment
137 Mine Chris: a voxel game as a ChrisOS integration workload Text floor met; technical review required Input routing, focus and capture; Desktop, windows and applications; ChrisC and the CLVM execution model; Software 3D renderer; Mine Chris graphics pipeline File Manager: ChrisOS Explorer
138 Doom port: bringing a real C game engine into ChrisOS Text floor met; technical review required ChrisC and the CLVM execution model; Input routing, focus and capture; 2D primitives and composition; ChrisFS architecture: layout, allocation, journaling and validation Mine Chris: a voxel game as a ChrisOS integration workload

09 · Geometry, rasterization and GPUs

Geometry and sampling

No. Chapter State Prerequisites Previous in sequence
139 Matrix transformations and coordinate spaces Text floor met; technical review required 2D primitives and composition Doom port: bringing a real C game engine into ChrisOS
140 Clipping, rejection and visibility boundaries Text floor met; technical review required Matrix transformations and coordinate spaces Matrix transformations and coordinate spaces
141 Triangle rasterization Text floor met; technical review required Clipping, rejection and visibility boundaries Clipping, rejection and visibility boundaries
142 Depth buffer Text floor met; technical review required Triangle rasterization Triangle rasterization
143 Textures Text floor met; technical review required Triangle rasterization Depth buffer
144 Software 3D renderer Text floor met; technical review required Textures; Depth buffer Textures
145 Parallel software rasterization Text floor met; technical review required Software 3D renderer; Kernel jobs and cooperative kernel threads Software 3D renderer

Device transport and commands

No. Chapter State Prerequisites Previous in sequence
146 VirtIO-GPU and VirGL Text floor met; technical review required Buses, memory-mapped I/O and DMA; Software 3D renderer Parallel software rasterization
147 VirtIO-GPU transport and resources Text floor met; technical review required Buses, memory-mapped I/O and DMA VirtIO-GPU and VirGL
148 Gfx3D backend-neutral API Text floor met; technical review required Software 3D renderer; VirtIO-GPU transport and resources VirtIO-GPU transport and resources
149 VirGL command stream Text floor met; technical review required Gfx3D backend-neutral API; VirtIO-GPU transport and resources Gfx3D backend-neutral API

Programmable shading

No. Chapter State Prerequisites Previous in sequence
150 Programmable shaders and Chris Shader IR Text floor met; technical review required Compiler construction pipeline in ChrisOS; Software 3D renderer; VirtIO-GPU and VirGL VirGL command stream
151 GLSL subset frontend Text floor met; technical review required Programmable shaders and Chris Shader IR; Compiler construction pipeline in ChrisOS Programmable shaders and Chris Shader IR
152 Chris Shader IR Text floor met; technical review required GLSL subset frontend GLSL subset frontend
153 TGSI backend Text floor met; technical review required Chris Shader IR; VirGL command stream Chris Shader IR
154 Software shader backend Text floor met; technical review required Chris Shader IR; Gfx3D backend-neutral API TGSI backend
155 Mine Chris graphics pipeline Text floor met; technical review required Textures; Clipping, rejection and visibility boundaries; Software 3D renderer Software shader backend

10 · Networks and protocol state

Frames, datagrams and streams

No. Chapter State Prerequisites Previous in sequence
156 Ethernet framing Text floor met; technical review required — Mine Chris graphics pipeline
157 IPv4 and addressing Text floor met; technical review required Ethernet framing Ethernet framing
158 UDP Text floor met; technical review required Ethernet framing; IPv4 and addressing IPv4 and addressing
159 TCP fundamentals and ChrisOS transfer path Text floor met; technical review required IPv4 and addressing UDP

ChrisOS network integration

No. Chapter State Prerequisites Previous in sequence
160 Network stack and VirtIO networking Text floor met; technical review required Buses, memory-mapped I/O and DMA; Interrupts and symmetric multiprocessing TCP fundamentals and ChrisOS transfer path
161 VirtIO-net Text floor met; technical review required Buses, memory-mapped I/O and DMA Network stack and VirtIO networking
162 Socket ownership and API Text floor met; technical review required TCP fundamentals and ChrisOS transfer path; UDP VirtIO-net

11 · Emulation and virtualization

Architectural semantics

No. Chapter State Prerequisites Previous in sequence
163 Machine emulation: architectural state, instruction steps and faults Text floor met; technical review required CPU datapath and instruction-set architecture; Buses, memory-mapped I/O and DMA; Virtual memory and address-space construction; Clocking, propagation delay and the meaning of time Socket ownership and API
164 x86-64 instruction decoding in ChrisCPU Text floor met; technical review required Machine emulation: architectural state, instruction steps and faults; x86 instruction encoding and bounded decoding; x86-64 registers, aliases and flags Machine emulation: architectural state, instruction steps and faults
165 Arithmetic flags and condition evaluation in ChrisCPU Text floor met; technical review required x86-64 instruction decoding in ChrisCPU; x86-64 registers, aliases and flags; Number systems and binary arithmetic x86-64 instruction decoding in ChrisCPU
166 Exceptions, interrupts and fault delivery in ChrisCPU Text floor met; technical review required x86-64 instruction decoding in ChrisCPU; Arithmetic flags and condition evaluation in ChrisCPU; x86-64 memory, privilege and architectural state Arithmetic flags and condition evaluation in ChrisCPU
167 Four-level paging and virtual-memory translation in ChrisCPU Text floor met; technical review required Exceptions, interrupts and fault delivery in ChrisCPU; x86-64 memory, privilege and architectural state; Virtual memory and address-space construction Exceptions, interrupts and fault delivery in ChrisCPU

ChrisVM platform

No. Chapter State Prerequisites Previous in sequence
168 ChrisVM and ChrisCPU Text floor met; technical review required Machine emulation: architectural state, instruction steps and faults; x86-64 memory, privilege and architectural state Four-level paging and virtual-memory translation in ChrisCPU
169 ChrisArchitectureState: the shared CPU-state contract Text floor met; technical review required ChrisVM and ChrisCPU; Four-level paging and virtual-memory translation in ChrisCPU; x86-64 registers, aliases and flags ChrisVM and ChrisCPU
170 ChrisMachine: ownership, lifecycle and platform boundaries Text floor met; technical review required ChrisArchitectureState: the shared CPU-state contract; ChrisVM and ChrisCPU ChrisArchitectureState: the shared CPU-state contract
171 ChrisVM physical memory map Text floor met; technical review required ChrisMachine: ownership, lifecycle and platform boundaries; Four-level paging and virtual-memory translation in ChrisCPU ChrisMachine: ownership, lifecycle and platform boundaries
172 ChrisVM port-I/O bus Text floor met; technical review required ChrisVM physical memory map; x86-64 instruction decoding in ChrisCPU ChrisVM physical memory map
173 ChrisVM MMIO bus Text floor met; technical review required ChrisVM physical memory map; ChrisMachine: ownership, lifecycle and platform boundaries ChrisVM port-I/O bus
174 Built-in ChrisVM devices Text floor met; technical review required ChrisVM port-I/O bus; ChrisVM MMIO bus ChrisVM MMIO bus
175 ChrisVM boot protocol v1 Text floor met; technical review required Built-in ChrisVM devices; ChrisArchitectureState: the shared CPU-state contract; Four-level paging and virtual-memory translation in ChrisCPU; ELF64, object linking and the ChrisOS kernel image Built-in ChrisVM devices
176 ChrisVM debugger and trace facilities Text floor met; technical review required ChrisVM boot protocol v1; ChrisVM and ChrisCPU ChrisVM boot protocol v1
177 Determinism and replay in ChrisVM Text floor met; technical review required ChrisVM debugger and trace facilities; ChrisArchitectureState: the shared CPU-state contract; Built-in ChrisVM devices ChrisVM debugger and trace facilities

Hardware virtualization

No. Chapter State Prerequisites Previous in sequence
178 Hardware virtualization and the ChrisHV boundary Text floor met; technical review required ChrisVM and ChrisCPU Determinism and replay in ChrisVM
179 Intel VMX and the future ChrisHV backend Text floor met; technical review required Hardware virtualization and the ChrisHV boundary; ChrisArchitectureState: the shared CPU-state contract; x86-64 memory, privilege and architectural state Hardware virtualization and the ChrisHV boundary
180 AMD SVM and the future ChrisHV backend Text floor met; technical review required Hardware virtualization and the ChrisHV boundary; ChrisArchitectureState: the shared CPU-state contract; x86-64 memory, privilege and architectural state Intel VMX and the future ChrisHV backend
181 EPT and NPT: second-level translation for ChrisHV Text floor met; technical review required Intel VMX and the future ChrisHV backend; AMD SVM and the future ChrisHV backend; Four-level paging and virtual-memory translation in ChrisCPU; ChrisVM physical memory map AMD SVM and the future ChrisHV backend

12 · Bootstrap, validation and research

Self-hosting

No. Chapter State Prerequisites Previous in sequence
182 Self-hosting and bootstrap Text floor met; technical review required Native toolchain: KCC, ChrisAsm, ChrisO and ChrisLd; Desktop, windows and applications EPT and NPT: second-level translation for ChrisHV
183 SH0-SH6 self-host evidence model Text floor met; technical review required Self-hosting and bootstrap Self-hosting and bootstrap
184 Compiler staging and convergence Text floor met; technical review required Self-hosting and bootstrap; SH0-SH6 self-host evidence model SH0-SH6 self-host evidence model
185 Internally produced kernel Text floor met; technical review required Self-hosting and bootstrap; Compiler staging and convergence Compiler staging and convergence
186 Reproducible builds and provenance Text floor met; technical review required Compiler staging and convergence; Internally produced kernel Internally produced kernel

Physical hardware

No. Chapter State Prerequisites Previous in sequence
187 Installation and real hardware Text floor met; technical review required Block storage stack; From power-on to kstart: the complete ChrisOS boot handoff Reproducible builds and provenance
188 GPT and EFI System Partition Text floor met; technical review required Installation and real hardware Installation and real hardware
189 UEFI disk boot: from firmware to the installed ChrisOS system Text floor met; technical review required Installation and real hardware; GPT and EFI System Partition; UEFI; Limine boot protocol GPT and EFI System Partition
190 ChrisOS hardware profile and evidence boundary Text floor met; technical review required UEFI disk boot: from firmware to the installed ChrisOS system; Installation and real hardware; x86-64 memory, privilege and architectural state UEFI disk boot: from firmware to the installed ChrisOS system
191 Bring-up diagnostics and failure localization Text floor met; technical review required ChrisOS hardware profile and evidence boundary; Validation, evidence classes and reliability ChrisOS hardware profile and evidence boundary
192 Driver compatibility: implementation, discovery and evidence Text floor met; technical review required ChrisOS hardware profile and evidence boundary; Bring-up diagnostics and failure localization; Validation, evidence classes and reliability Bring-up diagnostics and failure localization

Experiments and evidence

No. Chapter State Prerequisites Previous in sequence
193 Validation, evidence classes and reliability Text floor met; technical review required Kernel model, protection domains and trust boundaries Driver compatibility: implementation, discovery and evidence
194 Host-test architecture Text floor met; technical review required Validation, evidence classes and reliability Validation, evidence classes and reliability
195 QEMU gate architecture Text floor met; technical review required Host-test architecture; Validation, evidence classes and reliability Host-test architecture
196 Physical-hardware validation and hardware gates Text floor met; technical review required QEMU gate architecture; Driver compatibility: implementation, discovery and evidence; Bring-up diagnostics and failure localization QEMU gate architecture
197 Negative testing and fault injection Text floor met; technical review required Host-test architecture; QEMU gate architecture; Physical-hardware validation and hardware gates Physical-hardware validation and hardware gates
198 Fuzzing parsers and formats Text floor met; technical review required Host-test architecture; Negative testing and fault injection Negative testing and fault injection
199 Performance measurement Text floor met; technical review required Host-test architecture; QEMU gate architecture; Physical-hardware validation and hardware gates Fuzzing parsers and formats

Specifications and primary references

No. Chapter State Prerequisites Previous in sequence
200 Specifications, formats and revision policy Text floor met; technical review required — Performance measurement
201 ChrisVM specification Text floor met; technical review required Specifications, formats and revision policy; ChrisVM and ChrisCPU; ChrisArchitectureState: the shared CPU-state contract; ChrisMachine: ownership, lifecycle and platform boundaries Specifications, formats and revision policy
202 ChrisVM boot protocol v1 Text floor met; technical review required ChrisVM specification; ChrisVM boot protocol v1; ELF64, object linking and the ChrisOS kernel image; x86-64 memory, privilege and architectural state ChrisVM specification
203 ChrisO object format Text floor met; technical review required Specifications, formats and revision policy; ChrisO object format; ChrisLd ChrisVM boot protocol v1
204 ChrisFS on-disk format Text floor met; technical review required Specifications, formats and revision policy; ChrisFS architecture: layout, allocation, journaling and validation; Block storage stack ChrisO object format
205 CLVM executable and virtual-machine specification Text floor met; technical review required Specifications, formats and revision policy; CLVM bytecode format and instruction set; CLVM memory, allocation and isolation; CLVM syscalls and host-service ABI; CLVM interpreter architecture and execution model ChrisFS on-disk format
206 ChrisOS shader language and CSIR specification Text floor met; technical review required Specifications, formats and revision policy; GLSL subset frontend; Programmable shaders and Chris Shader IR; Gfx3D backend-neutral API CLVM executable and virtual-machine specification
207 Primary bibliography and standards map Text floor met; technical review required Specifications, formats and revision policy ChrisOS shader language and CSIR specification

Architecture history

No. Chapter State Prerequisites Previous in sequence
208 Architecture history and superseded evidence Text floor met; technical review required — Primary bibliography and standards map
209 Graphics architecture history Text floor met; technical review required Architecture history and superseded evidence Architecture history and superseded evidence
210 Native toolchain history Text floor met; technical review required Architecture history and superseded evidence Graphics architecture history
211 ChrisVM history Text floor met; technical review required Architecture history and superseded evidence Native toolchain history

Corpus maintenance

No. Chapter State Prerequisites Previous in sequence
212 Low-context documentation maintenance Text floor met; technical review required — ChrisVM history
213 Source and revision policy Text floor met; technical review required Low-context documentation maintenance Low-context documentation maintenance
214 Documentation schema and templates Text floor met; technical review required Low-context documentation maintenance Source and revision policy

13 · Development environment and contribution

Workstation and toolchain

No. Chapter State Prerequisites Previous in sequence
215 Developer Guide Text floor met; technical review required — Documentation schema and templates
216 Linux development environment Text floor met; technical review required Developer Guide Developer Guide
217 Windows and WSL2 development environment Text floor met; technical review required Developer Guide Linux development environment

Build, execution and validation

No. Chapter State Prerequisites Previous in sequence
218 Build, run and debug Text floor met; technical review required Developer Guide Windows and WSL2 development environment
219 Testing and validation Text floor met; technical review required Build, run and debug Build, run and debug
220 Development troubleshooting Text floor met; technical review required Build, run and debug Testing and validation

Contribution workflow

No. Chapter State Prerequisites Previous in sequence
221 Contribution workflow Text floor met; technical review required Testing and validation Development troubleshooting
Document record
ID: learning-path Class: generated-index